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How Hard Cores Fit In
When used in an ASIC chip, information about the hard core is entered at various stages to make room for it before its actual layers are added. With FPGAs, floor planning is still done, but the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.
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